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C8051T610/1/2/3/4/5/6/7
SFR Definition 22.2. SMB0CN: SMBus Control
Bit
Name
Type
Reset
7
MASTER
R
0
6
TXMODE
R
0
5
STA
R/W
0
4
STO
R/W
0
3
ACKRQ
R
0
2
ARBLOST
R
0
1
ACK
R/W
0
0
SI
R/W
0
SFR Address = 0xC0; Bit-Addressable
Bit Name Description
Read
Write
7
6
MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
TXMODE SMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
N/A
5
STA
SMBus Start Flag.
0: No Start or repeated
0: No Start generated.
Start detected.
1: Start or repeated Start
detected.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO
SMBus Stop Flag.
0: No Stop condition
0: No STOP condition is
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
ACKRQ
SMBus Acknowledge
0: No Ack requested
N/A
Request.
1: ACK requested
2
ARBLOST SMBus Arbitration Lost
Indicator.
0: No arbitration error.
1: Arbitration Lost
N/A
1
ACK
SMBus Acknowledge.
0: NACK received.
0: Send NACK
1: ACK received.
1: Send ACK
0
SI
SMBus Interrupt Flag.
This bit is set by hardware
0: No interrupt pending
1: Interrupt Pending
0: Clear interrupt, and initi-
ate next state machine
140
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
Rev 1.1
event.
1: Force interrupt.
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